1. Field of the Invention
The present invention relates to a PLL (Phase Lock Loop) circuit provided with a multiphase VCO (voltage-controlled oscillator)/ICO (current-controlled oscillator), particularly to a PLL circuit and a phase difference detecting circuit that can reduce phase pull-in time and adjust a skew at a higher precision.
2. Description of the Related Art
A device designed for reading out data stored in a DVD or a CD-ROM used in a personal computer or a video player is provided with a PLL circuit that operates in synchronism with an input signal called EFM, to generate a signal synchronized with the input signal. In such an apparatus, reduction of a pull-in time of the PLL circuit from entry of the input signal until becoming ready for reading out data is a critical factor to determine its performance. Also, in case where a phase difference between the input signal and a clock generated by the PLL circuit, i.e. a skew is large a reading error is prone to be caused, therefore it is essential for the PLL circuit to be capable of adjusting the skew at a high precision. For these reasons a PLL circuit and a phase difference detecting circuit that can reduce phase pull-in time and adjust a skew precisely and easily are being sought for.
Referring to operation of a conventional PLL circuit for phase-locking with an input signal, such method is known wherein a phase of a controlled oscillator (ICO) in which delay cells (delay elements, DCEL) are connected in a ring shape for oscillating multiphase signals is synchronized with an output of a separate reference clock oscillating circuit, so that one of the multiphase signals that is closest to a phase of the input signal is selected and output, out of the oscillation output. (Japanese Laid-open patent application No. 8-274629, Japanese Laid-open patent application No. 9-326692).
Likewise, such method utilizing a controlled oscillator (ICO) in which delay cells are connected in a ring shape is also known wherein phase lock by a PLL circuit is achieved through the steps of outputting a clock from a first stage of the controlled oscillator; feeding back the output in a form of a channel clock signal (channel clock) to a phase comparator for comparing the phase with the input signal; controlling an oscillating frequency of the controlled oscillator (ICO) with an output of the phase comparator, so that a phase difference between the input signal and the channel clock becomes minimal.
FIG. 13 is a schematic diagram showing a constitution of the latter PLL circuit. This PLL circuit is constituted of a phase comparator 1a for comparing a phase of an input signal and a channel clock, a charge pump circuit 2a to be controlled by an output of the phase comparator 1a, a low-pass filter (LPF filter) 3a for extracting a low frequency signal out of an output of the charge pump circuit 2a, a voltage/current converting circuit (VI converting circuit) 4a for converting an output of the LPF filter 3a into a current value, a controlled oscillator (ICO) 5a an oscillating frequency thereof is controlled by an output of the voltage/current converting circuit 4a and in which delay cells for outputting a plurality of multiphase signals are connected in a ring shape, a frequency dividing circuit 6a for dividing a frequency of a particular output out of the plurality of outputs of the controlled oscillator 5a to output the channel clock, a skew adjusting circuit 7a for inputting an advance signal and a delay signal and adding a control signal to the output of the charge pump circuit 2a, and a frequency fixing circuit 8a for controlling activation of the PLL circuit operation.
The PLL circuit according to FIG. 13 is designed to compare a phase of the input signal and of the channel clock at the phase comparator 1a and to feed back a phase difference signal (rising instruction signal and falling instruction signal) to the controlled oscillator (ICO) 5a through the charge pump circuit 2a, LPF filter 3a and voltage/current converting circuit 4a. The frequency fixing circuit 8a adds, prior to the above operation of the PLL circuit, a control current I_Fin to output current Iin of the voltage/current converting circuit 4a so that a frequency of the input signal and of the channel clock becomes equal and adjusts input current I_icoin of the controlled oscillator (ICO) 5a. Then once the frequency of the channel clock enters into a capture range of the phase comparator 1a, the frequency fixing circuit 8a outputs a PCSTART signal (from a low level toward a high level) to activate the phase comparator 1a, and maintains the control current I_Fin after outputting the PCSTART signal at a high level.
In such conventional PLL circuits provided with a controlled oscillator that oscillates multiphase signals, including both the former and the latter, an oscillating frequency of the controlled oscillator is analogically controlled by a phase difference output from the phase comparator through the LPF filter from the beginning of its action, therefore they have the problem that a long pull-in time is required before phase locking is achieved. Also, though a phase difference (skew) between the input signal and the controlled oscillator can be reduced by providing a skew adjusting circuit for controlling from outside, since the PLL circuit is not provided with means of generating a control signal (advance signal and delay signal) for skew adjustment, a high-precision skew adjustment is not feasible, and consequently it is impossible to successfully achieve the purpose required from a PLL circuit, i.e. a sufficiently high precision in the phase locking.
In view of the foregoing, it is an object of the invention to provide a PLL circuit and a phase difference detecting circuit capable of pulling in a phase at a high-speed.
It is another object of the invention to provide a PLL circuit and a phase difference detecting circuit that can perform a high-precision skew adjustment.